XILINX-DDR4-自定义componet（x8）-之一

1、MIG生成模板

Part type	Part name	Rank	StackHeight	CA Mirror	Data mask	Address width	Row width	Column width	Bank width	Bank group width	CS width	CKE width	ODT width	CK width	Memory speed grade	Memory density	Component density	Memory device width	Memory component width	Data bits per strobe	IO Voltages	Data widths	Min period	Max period	tCKE	tFAW	tFAW_dlr	tMRD	tRAS	tRCD	tREFI	tRFC	tRFC_dlr	tRP	tRRD_S	tRRD_L	tRRD_dlr	tRTP	tWR	tWTR_S	tWTR_L	tXPR	tZQCS	tZQINIT	tCCD_3ds	cas latency	cas write latency	burst length
Components	DDR4_CUSTOM	1	1	0	1	17	15	10	2	1	1	1	1	1	107E	4Gb	4Gb	16	16	8	1.2V	8,16,24,32,40,48,56,64,72,80	1071	1600	5000 ps	30000 ps	0	8 tck	34000 ps	13920 ps	7800000 ps	260000 ps	0	13920 ps	5300 ps	6400 ps	0	7500 ps	15000 ps	2500 ps	7500 ps	270 ns	128 tck	1024 tck	0	13	12	8
UDIMMs	DDR4_CUSTOM1	2	1	1	1	17	15	10	2	2	2	2	2	2	2G1	8GB	1Gb	72	8	8	1.2V	72	1250	1600	5000 ps	30000 ps	0	8 tck	34000 ps	13920 ps	7800000 ps	260000 ps	0	13920 ps	5300 ps	6400 ps	0	7500 ps	15000 ps	2500 ps	7500 ps	270 ns	128 tck	1024 tck	0	12	9	8
SODIMMs	DDR4_CUSTOM2	1	1	0	1	17	15	10	2	2	1	1	1	1	2G1	4GB	512Mb	64	8	8	1.2V	64	1071	1600	5000 ps	30000 ps	0	8 tck	34000 ps	13920 ps	7800000 ps	260000 ps	0	13920 ps	5300 ps	6400 ps	0	7500 ps	15000 ps	2500 ps	7500 ps	270 ns	128 tck	1024 tck	0	14	12	8
RDIMMs	DDR4_CUSTOM3	1	1	0	1	17	15	10	2	2	1	1	1	1	2G1	4GB	512Mb	72	8	8	1.2V	72	938	1600	5000 ps	30000 ps	0	8 tck	34000 ps	13920 ps	7800000 ps	260000 ps	0	13920 ps	5300 ps	6400 ps	0	7500 ps	15000 ps	2500 ps	7500 ps	270 ns	128 tck	1024 tck	0	15	11	8
RDIMMs	DDR4_CUSTOM4	2	2	1	1	17	15	10	2	2	2	2	2	1	83	8GB	4Gb	72	8	8	1.2V	72	833	1600	5000 ps	21000 ps	16 tck	8 tck	32000 ps	14160 ps	7800000 ps	350000 ps	100000 ps	14160 ps	3300 ps	4900 ps	4 tck	7500 ps	15000 ps	2500 ps	7500 ps	360 ns	128 tck	1024 tck	4 tck	16	14	8
RDIMMs	DDR4_CUSTOM5	2	4	1	0	17	16	10	2	2	2	2	2	1	83	16GB	4Gb	72	4	4	1.2V	72	833	1600	5000 ps	13000 ps	16 tck	8 tck	32000 ps	14160 ps	7800000 ps	350000 ps	110000 ps	14160 ps	3300 ps	4900 ps	4 tck	7500 ps	15000 ps	2500 ps	7500 ps	360 ns	128 tck	1024 tck	5 tck	16	14	8
LRDIMMs	DDR4_CUSTOM6	4	1	1	0	17	16	10	2	2	4	2	2	2	093E	32GB	8Gb	72	4	4	1.2V	72	938	1600	5000 ps	15000 ps	0	8 tck	33000 ps	14060 ps	7800000 ps	260000 ps	0	14160 ps	3300 ps	4900 ps	0	7500 ps	15000 ps	2500 ps	7500 ps	360 ns	128 tck	1024 tck	0	15	11	8

2、注意点

x8b的compnet。对应的data mask需要置为1

3、规则说明

After the CSV file has been imported, the custom memory part must be selected from the drop-down list in the MIG GUI to be used.

The user is responsible for ensuring that all memory parameter values (i.e. CL, CWL, Min/Max Period) and units (i.e. ps, ns etc.) are valid and entered correctly.

If a value is incorrect then you might not see the part listed in the drop-down list, or you might see hardware failures as a result of running an invalid or unsupported configuration.

For example, Only "Components", "UDIMMs", "RDIMMs", "SODIMMs", "LRDIMMs" are acceptable values for Part Type.

Make sure that all DRAM timing parameters values include the proper units and syntax. Please refer to the attached *.csv file examples as a reference.

DDR4 parts have the following valid ranges and limitations

• Rank is limited to 2 or 4 for LRDIMMs and 1 or 2 for all other devices.
• Stack Height is limited to 1, 2, or 4 for RIDIMMs, LRDIMMs, and Components and is 1 for all other devices .
  Note: This parameter is only used for 3DS parts and should be set to '1' when using non-3DS parts.
• CA Mirror is limited to "0" to disable or "1" to enable address mirroring.
  Note: CA Mirror can only be enabled for dual rank DIMMs and quad rank LRDIMMs
• Data mask is limited to "0" to disable or "1" to enable data mask.
  Note: Data mask cannot be enabled for x4 devices.
• Address width is limited to 17 for x8/x16 devices and 17 or 18 for x4 devices.
• Row width is limited to 14, 15, 16, 17, or 18.
• Column width is limited to 10.
• Bank width is limited to 2. (Listed as "Bank address in a bank group" for Micron parts).
• Bank Group width is limited to 1 for x16 devices and 2 for x4/x8 devices. (Listed as "Bank group address" in Micron parts).
• CS width is limited to 1 or 2 for components and DIMMs and 2 or 4 for LRDIMMs.
• CKE width is limited to 1 and 2.
• ODT width is limited to 1 and 2.
• CK width is limited to 1 and 2.
• Memory Speed grade is limited to the value defined in the memory vendor data sheet.
  Note: This value is for information purposes only and is not used by the IP.
• Memory density is limited to the value defined in the memory vendor data sheet.
  Note: This value is for information purposes only and is not used by the IP.
• Component density is limited to the value defined in the memory vendor data sheet.
  Note: This value is for information purposes only and is not used by the IP.
• Memory device width is limited to 4, 8, or 16 for components and 64 or 72 for DIMMs.
• Memory component width is limited to 4, 8, and 16.
• Data bits per strobe is limited to 4 and 8.
• I/O Voltage is limited to 1.2V.
• Data width is limited to 8, 16, 24, 32, 40, 48, 56, 64, 72, 80. 
  Note: Limited to a maximum of 9 components.
• Min period has a range between 750ps and 1600ps.
• Max period is limited to 1600ps.
• tCKE is limited to 5000ps.
• tFAW is limited to 10000-35000ps.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• tFAW_dllr is limited to 16 tck.
  Note: This parameter is only used for 3DS parts and should be set to '0' when using non-3DS parts.
• tMRD is limited to 8-10tck.
• tRAS is limited to 32000-35000ps.
• tRCD is limited to12500-15000ps.
• tREFI is limited to 975000-15600000ps.
• tRFC is limited to 90000-550000ps.
• tRFC_dlr is limited to 90000-120000 ps.
  Note: This parameter is only used for 3DS parts and should be set to '0' when using non-3DS parts.
• tRP is limited to 12500-15000ps.
• tRRD_S is limited to 2500-6000ps.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• tRRD_L is limited to 4900-7500ps.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• tRRD_dlr is limited to 4 tck.
  Note: This parameter is only used for 3DS parts and should be set to '0' when using non-3DS parts.
• tRTP is limited to 7500ps.
• tWR is limited to 15000ps.
• tWTR_S is limited to 2500ps.
• tWTR_L is limited to 7500ps.
• tXPR is limited to 100-560ns.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• tZQCS is limited to 128tck.
• tZQINIT is limited to 1024tck.
• tCCD_3ds is limited to 4-5 tck.
  Note: This parameter is only used for 3DS parts and should be set to '0' when using non-3DS parts.
• CAS Latency is limited to 9 to 24 but specific values can be obtained from the memory vendor data sheet.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• CAS Write Latency has a range between 9 to 20 but specific values can be obtained from the memory vendor data sheet.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• Burst Length is limited to 8.
• RTT (nominal) - ODT is limited to RZQ/6.
  Note: This parameter has been removed starting in the 2016.4 example CSV as the IP automatically defines this value based on slot and rank selection.

DDR3 parts have the following valid ranges and limitations:
 

• Rank is limited to 1 and 2 for components and most DIMMs and 4 for quad rank RDIMMs.
• CA Mirror is limited to "0" to disable or "1" to enable address mirroring.
  Note: CA Mirror can only be enabled for dual rank DIMMs and quad rank LRDIMMs
• Data mask is limited to "0" to disable or "1" to enable data mask.
  Note: Data mask cannot be enabled for x4 devices.
• Row width is limited to 12, 13, 14, 15, or 16.
• Column width is limited to 10, 11, or 12.
• Bank width is limited to 3.
• CS width is limited to 1 and 2 for components and most DIMMs and 4 for quad rank RDIMMs.
• CKE width is limited to 1 and 2.
• ODT width is limited to 1 and 2.
• CK width is limited to 1 and 2.
• Memory Speed grade is limited to the value defined in the memory vendor data sheet.
  Note: This value is for information purposes only and is not used by the IP.
• Memory density is limited to the value defined in the memory vendor data sheet.
  Note: This value is for information purposes only and is not used by the IP.
• Component density is limited to the value defined in the memory vendor data sheet.
  Note: This value is for information purposes only and is not used by the IP.
• Memory device width is limited to 4, 8, or 16 for components and 64 or 72 for DIMMs.
• Memory component width is limited to 4, 8, and 16.
• Data bits per strobe is limited to 4, and 8.
• I/O Voltage is limited to 1.35V and 1.5V.
  Note: Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for maximum supported data rates for 1.35V (DDR3L devices).
• Data width is limited to 8, 16, 24, 32, 40, 48, 56, 64, 72, 80.
  Note: Limited to a maximum of 9 components.
• Min period has a range between 938ps and 2500ps.
• Max period is limited up to 3300ps.
• tCKE is limited to 5000-20000ps.
• tFAW is limited to 25000-55000ps.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• tMRD is limited to 4tck.
• tRAS is limited to 33000-37500ps.
• tRCD is limited to 10000-15000ps.
• tREFI is limited to 3900000-7800000ps.
• tRFC is limited to 90000-350000ps.
• tRP is limited to 10000-15000ps.
• tRRD is limited to 5000-20000ps.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• tRTP is limited to 7500-20000ps.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• tWR is limited to 15000ps
• tWTR is limited to 7500-20000ps.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• tXPR is limited to 100-360ns.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• tZQCS is limited to 60-212ns
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• tZQINIT is limited to 480-1690ns.
• CAS Latency is limited to 5 to 14 but specific values can be obtained from the memory vendor data sheet.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• CAS Write Latency is limited to 5 to 10, but specific values can be obtained from the memory vendor data sheet.
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• Burst Length is limited to 8.
• RTT (nominal) - ODT is limited to RZQ/6.
  Note: This parameter has been removed starting in the 2016.4 example CSV as the IP automatically defines this value based on slot and rank selection.

RLDRAM3 parts have the following valid ranges and limitations:

• Data mask is limited to "0" to disable or "1" to enable data mask.
• Row width is limited to 19, 20, and 21.
• Bank width is limited to 4.
• CS width is limited to 1.
• CK width is limited to 1.
• Memory Speed grade is limited to 083E, 083F, 093, 093E, 107, 107E, 125, 125E, and 125F.
• Memory density is limited to 576Mb, and 1.125Gb.
• Memory device width is limited to 18 and 36.
• Data bits per strobe is limited to 9.
• I/O Voltages are limited to 1.2V.
• Data widths are limited to 18 or 36 for x18 devices and 36 or 72 for x36 devices.
• Min period has a range between 833ps and 1250ps.
• Max period is limited to 3333ps.
• Burst length is limited to 2, 4, and 8.
  Note: Burst Length 8 is not valid when using x36 parts.

QDRII+ parts have the following valid ranges and limitations:
 

• Memory Read Latency is limited to 2.0 and 2.5.
• Burst Length is limited to 2 and 4.
  Note: The Max Period is limited based on Burst Length.
  Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
• Address Width is limited to 17 through 25.
• Memory Speed Grade is limited to the value defined in the memory vendor data sheet.
  Note: This value is for information purposes only and is not used by the IP.
• Memory density is limited up to 144Mb.
  Note: The density should match the address width.
  Note: This value is for information purposes only and is not used by the IP.
• Memory device width is limited to 18 and 36.
• Data bits per strobe is limited to 18 and 36.
• I/O Voltage is limited to only "1.5V".
• Data widths limited to 18 or 36 for x18 devices and 36 for x36 devices.
• Min period has a range between 1580ps and 3000ps.
• Maximum period is limited to 8400ps.
• Note: Only Cypress parts are supported.
  • Cascaded data width is not supported for BL2 parts.
  • BL2 x18 parts only support 18 bit data width.
  • BL2 x36 parts only support 36 bit data width.

QDRIV parts have the following valid ranges and limitations:

• Performance type is limited to XP or HP.
  Note: The Max Period is limited based on Performance type. Refer to the UltraScale DC and AC Switching Characteristics Data Sheet for more information.
• Memory Read Latency is limited to 8 for XP parts and 5 for HP parts.
• Memory Write Latency is limited to 5 for XP parts and 3 for HP parts.
• Burst Length is limited to 2.
• Address Width is limited from 20 to 23.
• Memory Speed Grade is limited to the value defined in the memory vendor data sheet.
  Note: This value is for information purposes only and is not used by the IP.
• Memory density is limited up to 288Mb.
  Note: The density should match the address width.
  Note: This value is for information purposes only and is not used by the IP.
• Memory device width is limited to 18 and 36.
• Data bits per strobe is limited to 9.
  Note:  This parameter is always set to 9 regardless of the design configuration
• Data bits per dk is limited to 9 for x18 devices and 18 for x36 devices.
• I/O Voltage is limited to only "1.2V".
• Data widths limited to 18 for x18 devices and 36 for x36 devices.
• Min period has a range between 938ps to 3333ps.
• Maximum period is limited up to 3333 ps.
• Note: Only Cypress parts are supported.

LPDDR3 parts have the following valid ranges and limitations:

• Part type is limited to Components
• Rank is limited to 1 when cs width is 1
  Note: Rank was removed in 2017.2 and no longer required.
• Data mask is limited to 1
• Address width is limited to 10.
• Row width is limited to 13, 14, and 15.
• Column width is limited to 10 or 11 for x16 devices and 9 or 10 for x32 devices.
• Bank width is limited to 3.
• CS width is limited to 1.
  Note: CS width was removed in 2017.2 and no longer required.
• CKE width is limited to 1.
• ODT width is limited to 1.
• CK width is limited to 1.
• Memory Speed grade is limited to the value defined in the memory vendor data sheet. 
  Note: This value is for information purposes only and is not used by the IP.
• Memory density is limited to the value defined in the memory vendor data sheet. 
  Note: This value is for information purposes only and is not used by the IP.
• Component density is limited to the value defined in the memory vendor data sheet. 
  Note: This value is for information purposes only and is not used by the IP.
• Memory device width is limited to 16 or 32.
• Memory component width is limited to 16 or 32.
  Note: Memory component width was removed in 2017.2 and no longer required.
• Data bits per strobe is limited to 8.
• I/O Voltage is limited to 1.2V.
• Data width is limited to 16 for x16 devices or 32 for x32 devices.
  Note: Limited to a maximum of 1 component.
• Min period has a range between 938ps to 1250ps.
• Max period is limited up to 6000ps.
• tCKE is limited to 7500ps.
• tFAW is limited to 50000ps.
• tRAS is limited to 42000ps.
• tRCD is limited to 15000-24000ps.
• tREFI is limited to 7800000ps for 1Gb components and 3900000ps for 2Gb, 4Gb and 8Gb components.
• tREFIPB is limited to 975000ps for 1Gb components and 487500ps for 2Gb, 4Gb and 8Gb components.
• tRFC is limited to 13000ps for 1GB, 2Gb and 4Gb components and 21000ps for 8Gb components.
• tRFCAB is limited to 13000ps for 1Gb, 2Gb and 4Gb components and 21000ps for 8Gb components.
• tRFCPB is limited to 60000ps for 1Gb, 2Gb and 4Gb components and 90000ps for 8Gb components.
• tRP is limited to 15000 - 24000ps.
• tRPPAB is limited to 18000 - 27000ps.
• tRPPB is limited to 15000 - 24000ps.

tRRD is limited to 10000ps.

• tRTP is limited to 7500ps.
• tWR is limited to 15000ps.
• tWTR is limited to 7500ps.
  CAS Latency is limited to 6, 8, 9, 10, 11 and 12 but specific values can be obtained from the memory vendor data sheet. 
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• CAS Write Latency is limited to 3, 4, 5 and 6, but specific values can be obtained from the memory vendor data sheet. 
  Note: This value often has a range that varies with frequency.
  It is critical that this is entered correctly based on the target memory interface rate.
• Burst Length is limited to 8.

Note1: Using different OS language types can result in unintended characters being inserted into the CSV file which can prevent the custom part being imported into the MIG part list.

Note2: If you want to verify your values in the generated RTL, be aware that the RTLs units are clock cycles (tck).

参考链接：

63462 - UltraScale/UltraScale+ Memory IP - Sample CSV data file for creating Custom Parts