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[SC]SystemC在CPU/GPU验证中的应用（四）

news 2025/6/4 14:32:43

SystemC在CPU/GPU验证中的应用（四）

摘要：下面分享50个逐步升级SystemC编程能力的示例及建议的学习路线图。您可以一次一批地完成它们——从前五个基础的例子开始，然后转向channels, TLM, bus models, simple CPU/GPU kernels等等。在每个阶段掌握之后，再进行下一组的学习。

50个代表性的SystemC例子

Hello, SystemC! (module + sc_main)
Simple clock generator
4-bit up/down counter
Blocking FIFO channel
Non-blocking handshake channel
Combinational AND/OR modules
D-flip‐flop with async reset
8×1 multiplexer
Simple RAM model (blocking accesses)
Simple ROM model
Dual-port RAM
Bus arbiter (round-robin)
TLM2.0 blocking transport (initiator)
TLM2.0 blocking transport (target)
TLM2.0 non-blocking transport
TLM2.0 analysis port / export
Simple AXI-Lite bus model
AXI-Lite master + slave example
Quantum keeper & time annotation
tlm_utils::simple_initiator_socket
tlm_utils::simple_target_socket
Hierarchical module instantiation
Dynamic process spawn & kill
Event notification & sc_event_queue
Reset synchronization circuit
Clock domain crossing FIFO
Bus monitor / tracer (TLM analysis)
Memory-mapped register file
Interrupt controller model
Pipeline stage model (fetch/decode/execute)
Simple 4-stage CPU datapath
Cache model (direct-mapped)
DMA engine model
GPGPU kernel launcher skeleton
GPU shader core (vector add)
Barrier synchronization (sc_barrier emulation)
Producer-consumer with sc_mutex
sc_semaphore example
SystemC-AMS basic RC filter
Fixed-point arithmetic with sc_fixed
Power‐aware sc_trace (VCD generation)
Cross-trade-off analysis (timing vs. power)
SystemC assertions (SC_ASSERT)
UVM-SystemC basic use case
Co-simulation stub (Verilog DPI)
SystemC Python binding stub
Parameterized module (SC_MODULE_T)
TLM-2.0 generic payload extensions
Simple NoC router model
Full mini‐SOC: CPU + L2 cache + memory + interconnect

Fourth Batch: Examples 21–30

Below are the first five examples with complete code + detailed comments.

21. tlm_utils::simple_target_socket 示例

文件名：tlm_simple_target.cpp

#include <systemc>
#include <tlm>
#include <tlm_utils/simple_initiator_socket.h>
#include <tlm_utils/simple_target_socket.h>using namespace sc_core;
using namespace tlm;
using namespace std;// Initiator 模块：通过 simple_initiator_socket 发起读写事务
SC_MODULE(Initiator) {tlm_utils::simple_initiator_socket<Initiator> socket;SC_CTOR(Initiator): socket("socket"){SC_THREAD(thread_process);}void thread_process() {// 1) 写事务unsigned int data = 0xDEADBEEF;tlm_generic_payload txn;sc_time delay = SC_ZERO_TIME;txn.set_command(TLM_WRITE_COMMAND);txn.set_address(4);txn.set_data_ptr(reinterpret_cast<unsigned char*>(&data));txn.set_data_length(4);txn.set_streaming_width(4);cout << sc_time_stamp() << " Initiator: start WRITE\n";socket->b_transport(txn, delay);wait(delay);cout << sc_time_stamp() << " Initiator: WRITE done\n";// 2) 读事务data = 0;txn.set_command(TLM_READ_COMMAND);cout << sc_time_stamp() << " Initiator: start READ\n";socket->b_transport(txn, delay);wait(delay);cout << sc_time_stamp()<< " Initiator: READ data=0x" << hex << data << dec << "\n";sc_stop();}
};// Target 模块：通过 simple_target_socket 接收事务
SC_MODULE(Target) {tlm_utils::simple_target_socket<Target> socket;unsigned int mem[16];SC_CTOR(Target): socket("socket"){// 注册 b_transport 回调socket.register_b_transport(this, &Target::b_transport);// 初始化内存for (int i = 0; i < 16; ++i) mem[i] = i;}// Blocking transport 回调void b_transport(tlm_generic_payload& trans, sc_time& delay) {unsigned int addr = trans.get_address() / 4;unsigned char* ptr = trans.get_data_ptr();// 模拟访问延迟delay += sc_time(10, SC_NS);if (trans.is_write()) {unsigned int w = *reinterpret_cast<unsigned int*>(ptr);cout << sc_time_stamp()<< " Target: WRITE mem[" << addr << "]=" << w << "\n";mem[addr] = w;} else {unsigned int r = mem[addr];*reinterpret_cast<unsigned int*>(ptr) = r;cout << sc_time_stamp()<< " Target: READ  mem[" << addr << "]=" << r <<

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