8.31【Q】CXL-DMSim:

scons build/X86/gem5.opt-j16

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The simulator has been rigorously verified against a real hardware testbed with both FPGA- and ASIC-based CXL memory devices, which demonstrates the qualification of CXL-DMSim in simulating the characteristics of various CXL memory devices at an average simulation error of 3.4%. The experimental results using LMbench and STREAM benchmarks suggest that the CXL-FPGA memory exhibits a ∼2.88× higher latency than local DDR while the CXL-ASIC latency is ∼2.18×; CXL-FPGA achieves 45-69% of local DDR memory bandwidth, whereas the number for CXLASIC is 82-83%. The study also reveals that CXL memory can significantly enhance the performance of memory-intensive applications, improved by 23× at most with limited local memory for Viper key–value database and approximately 60% in memorybandwidth-sensitive scenarios such as MERCI

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stream 程序运行在NUMA节点0上，内存交错分配在DDR内存和CXL内存上，此时 stream 可获得二者的聚合带宽

numactl--cpunodebind=0--interleave=all ./stream

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Conventionally, remote direct memory access (RDMA) technology is exploited to realize memory disaggregation [5–9]. But RDMA is based on networking IO semantics which requires specialized NICs and software intervention, leading to a latency multiple orders of magnitude longer than that of local memory access

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